Tender Details

Country: USA
Summary: Customized CMOS Wafers Combined Sources Sought Notice and Notice of Intent to Sole Source
UST Ref No: 132119069
Deadline: 29 Dec 2025
Financier: Self Financed
Purchaser Ownership: Government
Tender Value: Refer Document
Notice Type: Tender
Document Ref. No.: NIST-SS26-CHIPS-55
Purchaser's Detail:
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Description:
***THIS IS A COMBINED SOURCES SOUGHT NOTICE AND NOTICE OF INTENT TO SOLE SOURCE***
The purpose of this sources sought notice is to conduct market research and identify potential sources of commercial products/services that satisfy the Government-s anticipated needs. If no alternate sources are identified, the Government intends to issue a Sole Source Award to Skywater Technology Foundry Inc, 2401 E 86th St, Bloomington, Minnesota, under the authority of FAR 13.106-1(b)(1)(i). The North American Industry Classification System (NAICS) code for this acquisition is 334413, Semiconductor and Related Device Manufacturing.
BACKGROUND
As part of the CHIPS R&D Program, the National Institute of Standards and Technology (NIST) requires the purchase of additional customized CMOS wafers based on a previously developed reticle set owned by NIST for a wafer-scale 0.13 um CMOS chip fabrication process. The CMOS wafers are designed to be used in developing a measurement and application testbed for novel electronic devices. Such an integrated measurement and application testbed is currently being used for parasitic-free novel device characterization as well as non-invasive imaging of complex circuits and systems. These wafers will be combined with the emerging memory technologies to allow for benchmarking the devices as stated in the initial proposal.
NIST is seeking information from sources that may be capable of providing a solution that will achieve the objectives described above, in addition to the following essential requirements:
Line Item 0001: Custom CMOS wafers
Quantity: 12
Technical Specifications:
Process flow shall be 0.13 um CMOS, Skywater FOSS SKY130 CMOS logic process node or equivalent
Process shall utilize the NIST owned tooling of the NIST Nanotechnology Xccelerator reticle set
The following mask/process options shall be used for the fabrication process:
Single-poly and up to six metal layers
Dual gate: 1.8 V core and 3.3 V...
Documents:

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Customized CMOS Wafers Combined Sources Sought Notice and Notice of Intent to Sole Source - USA Tender

The COMMERCE, DEPARTMENT OF | NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY, a Government sector organization in USA, has announced a new tender for Customized CMOS Wafers Combined Sources Sought Notice and Notice of Intent to Sole Source. This tender is published on USARFP under UST Ref No: 132119069 and is categorized as a Tender. Interested and eligible suppliers are invited to participate by reviewing the tender documents and submitting their bids before the deadline on 2025-12-29.

The estimated tender value is Refer Document, and full details, including technical specifications and submission requirements, are provided in the official tender documents. Ensure all submissions meet the criteria outlined to be considered for evaluation.